VLSI DESIGN LAB / 03
LOCAL CONSOLE · V1Tapeout,
without guesswork.
From RTL freeze to foundry handoff, this dependency-aware readiness board opens the next gate with evidence, not a status label.
WORKSPACE / PUBLIC-SAFELOCAL
Never enter names, customer data, NDA values, netlists, or paths. Use only public-safe aliases and summaries.
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dependency + owner + evidence verified
blocks, dependencies, missing proof
G0
DEPENDENCY LEDGER
Gate readiness board
Choose each state and record a public-safe owner and evidence note. Review receives 0.5 and Pass receives 1 only when all conditions are met.
SOURCE OF TRUTH
RTL Freeze
Freeze functions, interfaces, and exceptions to establish the reference point for downstream review.
- DEPENDS ON
- Start gate
- PROOF LENS
- release tag, lint/CDC summary, approved waiver reference
LOGIC INTEGRITY
Formal / LEC
Check post-synthesis equivalence and key properties to show that logic transformation preserved intent.
- DEPENDS ON
- RTL Freeze
- PROOF LENS
- equivalence summary, property coverage, unresolved cone note
TEST READINESS
DFT
Close scan, compression, MBIST, and test-mode readiness for manufacturing test.
- DEPENDS ON
- Formal / LEC
- PROOF LENS
- scan coverage, rule-check summary, test-mode constraint note
PHYSICAL IMPLEMENTATION
P&R
Track congestion and physical constraints from floorplan through route to produce a review-ready database.
- DEPENDS ON
- DFT
- PROOF LENS
- route summary, congestion snapshot reference, final database tag
ELECTRICAL SIGN-OFF
STA / SI / EMIR
Check timing, noise, and power-integrity risk against budgets across all required corners.
- DEPENDS ON
- P&R
- PROOF LENS
- corner matrix, WNS/TNS summary, SI and EMIR exception log
FOUNDRY HANDOFF
DRC / LVS
Verify manufacturing rules and circuit equivalence for final layout and seal the release artifacts.
- DEPENDS ON
- STA / SI / EMIR
- PROOF LENS
- DRC/LVS summary, approved waiver IDs, stream-out checksum