DESIGN LAB / 04 · OPEN PPA ATLAS
SYNTHETIC DEMOTurn design intuition
into a verifiable map.
Read performance, area, and power together and trace the generation context behind every point. Every design name and value currently shown is synthetic demonstration data—not an observed benchmark result.
- VISIBLE RUNS
- 08 all synthetic
- DESIGN FAMILIES
- 04 fictional RTL
- PUBLICATION RULE
- PROOF or it stays private
To prevent confusion with observed results, every value—including design, PDK, commit, and runtime—is explicitly labeled fictional or synthetic.
ATLAS / 01
PPA design space
Performance increases to the right and cost increases upward. Highlighted points are synthetic Pareto candidates not dominated within the current view.
Carries filters, axes, value mode, and selected synthetic run. The frozen benchmark dataset is never duplicated.
8 points visible4 Pareto candidates
Every point is a synthetic demo run. Select a point to open provenance details. Pareto candidates are marked P.
- Haetae-RV32 · 28 nm
- Goryeo-AES · 28 nm
- Nuri-Tensor · 28 nm
- Dokkaebi-NoC · 45 nm
Pareto status is computed only against visible points in the same workload. It does not demonstrate technical superiority.
VISIBLE SET / 02
Synthetic within-workload comparison
PPA index = performance ÷ √(area × power), with each family baseline = 100. Ordinals reset for every workload and never form a global product ranking.
| GROUP # | Design / run | Workload | Node | Target clock | Area | Power | PPA idx | Source |
|---|---|---|---|---|---|---|---|---|
| CPU core · ranked only inside this workload | ||||||||
| 01 | CPU core | 28 nm | 780 MHz | 0.91 mm² | 34.8 mW | 138 | SYNTHETIC | |
| 02 | CPU core | 45 nm | 590 MHz | 1.36 mm² | 41.2 mW | 100 | SYNTHETIC | |
| Crypto · ranked only inside this workload | ||||||||
| 01 | Crypto | 28 nm | 1,180 MHz | 0.43 mm² | 19.7 mW | 150 | SYNTHETIC | |
| 02 | Crypto | 45 nm | 810 MHz | 0.74 mm² | 24.6 mW | 100 | SYNTHETIC | |
| AI MAC array · ranked only inside this workload | ||||||||
| 01 | AI MAC array | 28 nm | 690 MHz | 3.14 mm² | 184 mW | 155 | SYNTHETIC | |
| 02 | AI MAC array | 65 nm | 340 MHz | 7.38 mm² | 258 mW | 100 | SYNTHETIC | |
| Interconnect · ranked only inside this workload | ||||||||
| 01 | Interconnect | 45 nm | 930 MHz | 2.08 mm² | 67.5 mW | 140 | SYNTHETIC | |
| 02 | Interconnect | 65 nm | 510 MHz | 3.96 mm² | 92.4 mW | 100 | SYNTHETIC | |
Clock, area, power, runtime, and PPA index in every row are generated for UI demonstration. Do not cite them or use them as real process performance. This Atlas is not an EDA sign-off tool or investment advice.
PUBLICATION GATE / 03
Publish evidence before numbers.
01Do not publish observed values without verified PDK and library conditions.
02Do not rank results without a reproducible flow commit and constraints.
03Always separate synthetic examples visually from observed data.