VLSI Korea

05 METHODS & LIMITS

Equations and limits
belong in the interface.

Design Lab is an open collection for education and preliminary judgment. It does not collect inputs or produce commercial sign-off results.

01

Timing Studio

Parses startpoint, endpoint, path rows, arrival, required time, and slack from report text in the browser. Sensitivity uses the explicit budget: period − uncertainty − setup − arrival.

02

Floorplan Arena

The score is a weighted combination of overlap, boundary, HPWL, and a congestion proxy. It trains floorplan trade-offs; it is not a manufacturable placement or router result.

03

Tapeout Console

Stores gate dependencies and state locally and exports an evidence bundle. It never replaces an organization's official release, review, or waiver process.

04

Open PPA Atlas

Every current value is labeled SYNTHETIC DEMO. Public observed results are added only when design, PDK, node, constraints, tool commit, and source are verified together.

05

Portable experiment capsule

Timing, Economics, Floorplan, Tapeout, and PPA use the same versioned .vlsilab.json envelope. Files never leave the browser, are capped at 64 KB, and must pass schema, tool, number, shape, and disclosure validation. Timing omits raw reports and identifiers; Tapeout omits aliases, schedules, owners, and evidence.

INPUTBrowser-local processing

No server upload, account, or input telemetry

DATAPublic and synthetic only

No employer, customer, NDA, netlist, or proprietary reports

OUTPUTReviewable exports

Save equations, state, and provenance together

USEEducation and early review

Not investment advice; never replaces qualified review or sign-off